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rad-hard sram 288mb/144mb/72mb burst of 2 sigmaquad-ii+ tm 350 mhz?250 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump ccga military temp rev: 1.01 7/2017 1/30 ? 2017, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs82612qt19/37c e-350m/250m gs81332qt19/37ce-350m/250m gs8692qt19/37ce-350m/250m preliminary features ? aerospace-level product ? 2.0 clock latency ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? dual-range on-die terminat ion (odt) on data (d), byte write ( bw ), and clock (k, k ) inputs ? burst of 2 read and write ? 1.8 v +100/C100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? data valid pin (qvld) supp ort ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump ceramic column grid array (ccga) package radiation performance ? total ionizing dose (tid) > 200krads(si) ? soft error rate (ser) = tbr ? neutrons = tbr ? single event latchup immunity > 80 mev.cm 2 /mg (100 ? c) sigmaquad ? family overview the gs82612qt19/37ce, gs81332qt19/37ce, and gs8692qt19/37ce are built in compliance with the sigmaquad-ii+ sram pinout standard for separate i/o synchronous srams. they are 301,989,888-bit (288mb), 150,994,944-bit (144mb), and 75,497,472-bit (72mb) srams. these sigmaquad sr ams comprise a family of low power, low voltage hstl i/ o radiation-hard ened (rad-hard) srams designed to operate in high radiation environments. clocking and addr essing schemes the rad-hard sigmaquad-i i+ srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer . each internal read and write ope rat ion in a sigmaquad-ii+ b2 ram is two times wider than the device i/o bus. an input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. an output data multiplexer is used to cap ture the data produced from a single memory array read and th en route it to th e appropriate output drivers as needed. ther efore, the addre ss field of a sigmaquad-ii+ b2 ram is always one address pin less than the advertised index depth (e.g., the 8m x 36 has an 4m addressable index). parameter synopsis -350m -250m tkhkh 2.86 ns 4.0 ns tkhqv 0.45 ns 0.45 ns
16m x 18 sigmaquad-ii+ sram?top view (288mb) 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w bw1 k sa r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm bo dy?1 mm bump pitch note: bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 2/30 ? 2017, gsi technology preliminary
8m x 36 sigmaquad-ii+ sr am?top view (288mb) 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w bw2 k bw1 r sa sa cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump ccga?21 x 25 mm bo d y?1.27 mm bump pitch (tbr) note: bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 3/30 ? 2017, gsi technology preliminary
8m x 18 sigmaquad-ii+ sr am?top view (144mb) 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w bw1 k nc (288mb) r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm bo dy?1 mm bump pitch note: bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 4/30 ? 2017, gsi technology preliminary
4m x 36 sigmaquad-ii+ sr am?top view (144mb) 1 2 3 4 5 6 7 8 9 10 11 a cq nc (288mb) sa w bw2 k bw1 r sa sa cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump ccga?21 x 25 mm bo d y?1.27 mm bump pitch (tbr) note: bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 5/30 ? 2017, gsi technology preliminary
4m x 18 sigmaquad-ii+ sram?top view (72mb) 1 2 3 4 5 6 7 8 9 10 11 a cq nc (144mb) sa w bw1 k nc (288mb) r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm bo dy?1 mm bump pitch note: bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 6/30 ? 2017, gsi technology preliminary
2m x 36 sigmaquad-ii+ sram?top view (72mb) 1 2 3 4 5 6 7 8 9 10 11 a cq nc (288mb) sa w bw2 k bw1 r sa nc (144mb) cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump ccga?21 x 25 mm bo d y?1.27 mm bump pitch (tbr) note: bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 7/30 ? 2017, gsi technology preliminary
pin description table symbol description type comments sa synchronous address inputs input ? r synchronous read input active low w synchronous write input active low bw0 ? bw3 synchronous byte writes input active low k input clock input active high k input clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? qn synchronous data outputs output ? dn synchronous data inputs input ? doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 v or 1.5 v nominal v ss power supply: ground supply ? qvld q valid output output ? odt on-die termination input low = low impedance range high/float = high impedance range nc no connect ? ? gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 8/30 ? 2017, gsi technology preliminary notes: 1. nc = not connected to die or any other pin 2. when zq pin is directly connected to v ddq , output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. k and k cannot be set to v ref voltage.
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 9/30 ? 2017, gsi technology preliminary
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 10/30 ? 2017, gsi technology preliminary background separate i/o srams, from a system architecture point of view, a re attractive in applications where alternating reads and write s are needed. therefore, the sigmaquad-ii+ sram interface and truth t able are optimized for alternating reads and writes. separate i /o srams are unpopular in applications where multiple reads or mul tiple writes are needed because burst read or write transfers f rom separate i/o srams can cut the rams bandwidth in half. sigmaquad-ii b2 sram ddr read the read port samples the stat us of th e address input and r pins at each rising edge of k. a low on the read enable-bar pin, r , begins a read cycle. clocking in a high on the read enable-bar pin, r , begins a read por t deselect cycle. sigmaquad-ii b2 sram ddr write the write port samples the status of the w pin at each rising edge of k and the address inpu t pins on the following rising edge of k . a low on the write enable-bar pin, w , begins a write cycle. the first of the da ta-in pairs associat ed with the write command is clocked in with the same rising edge of k used to capture the w rite command. the second of the two data in transfers is captur ed on the rising edge of k along with the write address. clocking in a high on w causes a write port deselect cycle. special functions byte write control byte write enable pins are sampl ed at the same time that data in is sampled. a high on the byte write enable pin associated wi th a particular byte (e.g., bw0 controls d0Cd8 inputs) will inh ibit the storage of that partic ular byte, leaving wh atever data may be stored at the current address at that byte location undisturbed. any or all of the byte write enable pins may be driven high o r low during the data in sample times in a write sequence. each write enable command and wr ite addres s loaded into the ram provides the base address for a 2beat data tran sfer. the x18 version of the ram, for example, may write 36 bits in associati on with each address loaded. any 9-bit byte may be masked in an y write sequence. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 written unchanged unchanged written beat 1 beat 2
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 11/30 ? 2017, gsi technology preliminary flxdrive-ii output driver impedance control +67/,26ljpd4xdg,,65$0vduh vxssolhgzlwksurjudppdeohlps hgdqfhrxwsxwgulyhuv7kh= 4slqpxvweh frqqhfwhgwr 9 66 ylddqh[whuqdouhvlvwru54wr doorzwkh65$0wrprqlwrudqg dgmxvwlwvrxwsxwgulyhulpshgd qfh7khydoxhri54pxvweh ;wkhydoxhriwkhghvluhg5$0rxwsxwlpshgdqfh7khdoorzdeoh udqjhri54wrjxdudqwhhlpshgdqfhpdwfklqjfrqwlqxrxvo\lv ehwzhhq : dqg : 3hulrglfuhdgmxvwphqwriwkh rxwsxwgulyhulpshgdqfhlvqhfhv vdu\dvwkhlpshgdqfh lvdiihfwhge\guliwv lqvxsso\yrowdjhdqgwhpshudwx uh7kh65$0?v rxwsxwlpshgdqfh flufxlwu\frpshqvdwhviru guliwvlqvxsso\yrowdjhdqg whpshudwxuh$forfnf\fohfrxqw hushulrglfdoo\wuljjhuvdqlps hgdqfhhydoxdwlrquhvhwvdqg frxqwvdjdlq(dfklpshgdqfh hydoxdwlrqpd\pryhwkhrxwsxwg ulyhulpshgdqfhohyhorqhvwhs dwdwlphwrzdugvwkhrswlpxpo hyho7khrxws xwgulyhulv lpsohphqwhgzlwkglv fuhwhelqdu\zhljkwhglpshgdqfhvwhsv input termination impedance control 7khvh6ljpd4xdg,,65$0vduhvx ssolhgzlwksurjudppdeohlqsxw whuplqdwlrqrq'dwd'%\wh:ulwh %: dqg&orfn. . lqsxwuhfhlyhuv7khlqsxwwhupl qdwlrqlvdozd\vhqdeohgdqgw khlpshgdqfhlvsurjudpphgyldwk hvdph54uhvlvwrufrqqhfwhg ehwzhhqwkh=4slqdqg9 66 xvhgwrsurjudprxwsxwgulyhu lpshgdqfhlqfrqmxfwlrqzlwkw kh2'7slq5:khqwkh2'7slq lvwlhg/rzlqsxwwhuplqdwlrqlvvwurqjlhorzlpshgdqfh dqglvqrplqdoo\htxdowr54 7khyhqlqhtxlydohqwzkhq54 lv ehwzhhq dqg :khqwkh2'7slqlvwlhg+ljkruohiwi ordwlqj2wkhslqkdvdvpdoosxooxsuhvlvwrulqsxwwhuplqdwlr q lvzhdnlhkljklpshgdqfh dqglvqrplqdoo\htxdowr54 7khyhqlqhtxlydohqwzkhq5 4lvehwzhhq dqg 3hulrglfuhdgmxvwphqwriwkhwhup lqdwlrqlpshgdqfhrffxuvwrfr pshqvdwhiruguliwvlqvxsso\yrowdjhdqgwhpshudwxuhlqwkhv dph pdqqhudvirugulyhul pshgdqfhvhhderyh note: its shol alas e rie ih or o the shol eer e tristate ie i a ih state the its are tristate the it teriatio ill ll the sial to ie to the sitch oit o the ia receier hich col case the receier to eter a etast ale state reslti i the rec eier cosi ore oer tha it orall ol his col r eslt i the eices oerati crrets ei hiher power-up initialization $iwhusrzhuxsvwdeohlqsxwforfnvpxvwehdssolhgwrwkhghyl fhiru p vsulruwrlvvxlqjuhdgdqgzulwhfrppdqgv6hhwkhw .,qlw wlplqjsdudphwhulqwkh ac electrical characteristics sectio note: he t it reireet is ieeet o t he toc reireet hich se ciies ho a ccles o stale it clocs st e alie ater the o i has ee rie ih i orer to esre that the locs roerl a the st loc roerl eore issi rea a rite coas oeer t it is reater tha t oc ee at the sloest eritte ccle tie o s s s coseetl the s associate ith t it is siciet to coer the t oc reireet at oer i the o i is rie ih rior to the start o the s erio also t it ol ees to e et oce ie iatel ater oer hereas t oc st e et a tie the is isalereset hether toli o o or stoi clocs or s
separate i/o sigmaquad- ii b2 sigmaquad-ii sr am read truth table a r output next state q q k ? (t n ) k ? (t n ) k ? (t n ) k ? (t n+2 ) k ? (t n+2? ) x 1 deselect hi-z hi-z v 0 read q0 q1 notes: 1. x = don?t care, 1 = high, 0 = low, v = valid. 2. r is evaluated on the rising edge of k. 3. q0 and q1 are the first and second data output transfers in a read. separate i/o sigmaquad- ii b2 sigmaquad-ii sr am write truth table a w bwn bwn input next state d d k ? (t n + ? ) k ? (t n ) k ? (t n ) k ? (t n + ? ) k ??? k ? (t n ), (t n + ? ) k ? (t n ) k ? (t n + ? ) v 0 0 0 write byte dx0, write byte dx1 d0 d1 v 0 0 1 write byte dx0, write abort byte dx1 d0 x v 0 1 0 write abort byte dx0, write byte dx1 x d1 x 0 1 1 write abort byte dx0, write abort byte dx1 x x x 1 x x deselect x x notes: 1. x = don?t care, h = high, l = low, v = valid. 2. w is evaluated on the rising edge of k. 3. d0 and d1 are the first and second data input transfers in a write. 4. bwn represents any of the byte write enable inputs ( bw0 , bw1 , etc.). gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 12/30 ? 2017, gsi technology preliminary
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 13/30 ? 2017, gsi technology preliminary x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( d 2.9 v max.) v v in input voltage (address, control, data, clock) ?0.5 to v ddq +0.5 ( d 2.9 v max.) v v tin input voltage (tck, tms, tdi) ?0.5 to v ddq +0.5 ( d 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?65 to 150 (tbr) o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 14/30 ? 2017, gsi technology preliminary recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref v ddq /2 ? 0.05 ? v ddq /2 + 0.05 v note: the power supplies need to be powered up simult aneo usly or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . for more information, read an1021 sigmaquad and sigmaddr power-up. operating temperature parameter symbol min. typ. max. unit junction temperature t j ?55 25 125 qc
thermal impedance package test pcb substrate ??ja (c/w) airflow = 0 m/s ? ja (c/w) airflow = 1 m/s ? ja (c/w) airflow = 2 m/s ??jb (c/w) ? jc (c/w) 165 ccga 4-layer (tbr) n/a n/a n/a tbd tbd notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature. hstl i/o dc input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.05 v ddq /2 + 0.05 v ? input high voltage v ih1 v ref + 0.1 v ddq + 0.3 v 1 input low voltage v il1 ?0.3 v ref ? 0.1 v 1 input high voltage v ih2 0.7 * v ddq v ddq + 0.3 v 2,3 input low voltage v il2 ?0.3 0.3 * v ddq v 2,3 notes: 1. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 2. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 3. parameters apply to zq during jtag boundary scan testing only. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 15/30 ? 2017, gsi technology preliminary hstl i/o ac input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.08 v ddq /2 + 0.08 v ? input high voltage v ih1 v ref + 0.2 v ddq + 0.5 v 1,2,3 input low voltage v il1 ?0.5 v ref ? 0.2 v 1,2,3 input high voltage v ih2 v ddq ? 0.2 v ddq + 0.5 v 4,5 input low voltage v il2 ?0.5 0.2 v 4,5 notes: 1. v ih(max) and v il(min) apply for pulse widths less than one-quarter of the cycle time. 2. input rise and fall times must be a minimum of 1 v/ns, and within 10% of each other. 3. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 4. parameters apply to d off , odt during normal operation an d jtag boundary scan testing. 5. parameters apply to zq during jtag boundary scan testing only.
capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. ac test conditions parameter conditions input high level 1.25 input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 16/30 ? 2017, gsi technology preliminary dq vt = = 0.75 v 50? rq = 250 ?? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i il doff v in = 0 to v dd ?2 ua 100 ua odt i il odt v in = 0 to v dd ?100 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 17/30 ? 2017, gsi technology preliminary programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175? ?? rq ? 350 ??? 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? ? rq ? 350?? . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v 4. 0 ???? rq ? ?? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma
operating currents parameter symbol test conditions -350m -250m unit notes C55 to 125c C55 to 125c operating current (x36): ddr i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 1430 1140 ma 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 1280 1030 ma 2, 3 standby current (nop): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs ?? 0.2 v or ?? v dd ? 0.2 v 590 520 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated wi t h 50% read cycles and 50% write cycles. 4. standby current is only after all pending re ad and write burst operations are completed. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 18/30 ? 2017, gsi technology preliminary
ac electrical characteristics parameter symbol -350m -250m units notes min max min max clock k, k clock cycle time t khkh 2.86 8.4 4.0 8.4 ns tk variable t kvar ? 0.2 ? 0.2 ns 4 k, k clock high pulse width t khkl 0.4 ? 1.6 ? cycle k, k clock low pulse width t klkh 0.4 ? 1.6 ? cycle k to k high t kh k h 1.13 ? 1.8 ? ns k to k high t k hkh 1.13 ? 1.8 ? ns dll lock time t klock 2048 ? 2048 ? cycle 5 k static to dll reset t kreset 30 ? 30 ? ns k, k clock initialization t kinit ? s 6 output times k, k clock high to data output valid t khqv ?0.45 ? ?0.45 ? ns k, k clock high to data output hold t khqx ? 0.45 ? 0.45 ns k, k clock high to echo clock valid t khcqv ?0.45 ? ?0.45 ? ns k, k clock high to echo clock hold t khcqx ? 0.23 ? 0.30 ns cq, cq high output valid t cqhqv ?0.23 ? ?0.30 ? ns cq, cq high output hold t cqhqx ?0.23 0.23 ?0.30 0.30 ns cq, cq high to qvld t qvld 1.08 ? 1.55 ? ns cq phase distortion t cqh cq h t cq hcqh ? 0.45 ? 0.45 ns k clock high to data output high-z t khqz ?0.45 ? ?0.45 ? ns k clock high to data output low-z t khqx1 ns setup times address input setup time t avkh 0.4 ? 0.35 ? ns 1 control input setup time ( r , w ) t ivkh 0.28 ? 0.35 ? ns 2 control input setup time ( bwx ) ( bwx ) t ivkh 0.28 ? 0.35 ? ns 3 data input setup time t dvkh ns hold times address input hold time t khax 0.4 ? 0.35 ? ns 1 control input hold time ( r , w ) t khix 0.28 ? 0.35 ? ns 2 control input hold time ( bwx ) ( bwx ) t khix 0.28 ? 0.35 ? ns 3 data input hold time t khdx 2.86 8.4 4.0 8.4 ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are r , w 3. control signals are bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 4. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 6. after device power-up, 20 ? s of stable input clocks (as specified by t kinit ) must be supplied before reads and writes are issued. gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 19/30 ? 2017, gsi technology preliminary
read nop cq-based timing diagram read a0 / write nop read a1 / write nop read a2 / write nop read a3 / write nop noop noop noop a0 a1 a2 a3 q0 q0+1 q1 q1+1 q2 q2+1 q3 q3+1 tqvld tcqlqx tcqhqx tcqhqv tcqlqv tqvld tcqhqx tcqlqx tcqlqv tcqhqv tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w qvld q cq cq gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 20/30 ? 2017, gsi technology preliminary
read-write cq-based timing diagram read a0/ write a8 read a1/ write a7 read a2/ write a6 read a3/ write a5 noop noop noop a0 a8 a1 a7 a2 a6 a3 a5 d8 d8+1 d7 d7+1 d6 d6+1 d5 d5+1 q0 q0+1 q1 q1+1 q2 q2+1 q3 q3+1 tqvld tcqhqx tcqhqv tcqlqx tcqlqv tqvld tcqlqx tcqlqv tcqhqx tcqhqv tkhdx tdvkh tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh tkhax tavkh k k addr r w bwx d qvld q cq cq gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 21/30 ? 2017, gsi technology preliminary
write nop timing diagram read no-op / write a0 read no-op / write a1 read no -op / write a2 read no-op / write a3 no-op no-op no-op a0 a1 a2 a3 d0 d0+1 d1 d1+1 d2 d2+1 d3 d3+1 tkhdx tdvkh tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w bwx d gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 22/30 ? 2017, gsi technology preliminary
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 23/30 ? 2017, gsi technology preliminary jtag port operation overview the jtag port on this ram operate s in a manner th at is complian t with ieee standard 1149.1-1 990, a serial boundary scan interface standard (commonly refe rred to as jtag). the jtag por t input interface le vels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device w ithout utilizing the jtag po rt. the port is reset at power-up and will remai n inactive unle ss clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal opera tion of the ram with the jtag port unused, tck, tdi, and tms ma y be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the fa lling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state m achine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed b etween tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the fa lling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag regist ers, refered to as t es t access port or t ap registers, are selected (one a t a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register t hat captures serial input data on the rising edge of tck and pushes serial data out on the next fall ing edge of tck. when a register is selected, it is placed betw een the tdi and tdo pins. instruction register the instruction register holds the instructions that are execut ed by the tap controller when it is moved into the run, test/id le, or the various data register states . instructions are 3 bits long. the instruction register can be loaded when it i s placed between the tdi and tdo pins. the instruction register is automatically pre loaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed b etween tdi and tdo. it allows serial test data to be passed t hrough the rams jtag port to anothe r device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a co llection of flip flops that c an be preset by the logic level found on the rams input or i/o pins. the flip flops are then daisy ch ained together so the levels fo und can be shifted serially out o f the jtag ports tdo pin. th e boundary scan register also incl udes a number of place holder flip flops (always set to a logi c 1). the relationship between the device pins and the bits in the boundary scan register is descr ibed in the scan ord er table following. the boundary scan
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 24/30 ? 2017, gsi technology preliminary register, under the control of t he tap controller, is loaded wi th the contents of the rams i/o r ing when the controller is in capture-dr state and then is placed between the tdi and tdo pin s when the controller is moved to shift-dr state. sample-z, sample/preload and extest instruct ions can be used to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 12 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a devi ce and ven dor specific 32-bit code when the controller is put i n capture-dr state with the idcode command loaded in the instruct ion register. the code is load ed from a 32-bit on-chip rom. it describes various attributes o f the ram as indicated below. the register is then placed betw een the tdi and tdo pins when t he controller is moved into shift-dr state. bit 0 in the register is the lsb and the f irst to reach tdo when shifting begins. id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 25/30 ? 2017, gsi technology preliminary tap controller instruction set overview there are two classes of in structions defined in the standard 1 149.1-1990; the standard (public) instructions, and device spec ific (private) instructions. some publ ic instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. t he tap on this device may be u sed to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in c apture-ir state the two l east significant bits of the inst ruction register are loaded wi th 01. when the controller is moved to the shift-ir state the instruct ion register is placed between tdi and tdo. in this state the d esired instruction is serially loaded t hrough the tdi input (while the previous contents are shifted out at tdo). for all instruction s, the tap executes newly loaded instructions only when the controller is moved to update-ir state. th e tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction regist er the bypass register is placed between tdi and tdo. this occurs when the tap co ntroller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other dev ices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instructio n . when the sample / preload instruction is
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 26/30 ? 2017, gsi technology preliminary loaded in the instruction regist er, moving the tap controller i nto the capture-dr state loads t he data in the rams input and i/o buffers into the boundary scan register. boundary scan regi ster locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary sc an chain table at the end of this section of the datasheet. bec ause the ram clock is independent from the tap clock (tck) it is pos sible for the tap to attempt to capture the i/o ring contents while the input buffers are in t ransition (i.e. in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, r epeatable results can not be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up pl us hold time (tts plus tth). t he rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the bound ary scan register. moving the c ontroller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instr uction register is loaded with all logic 0s. the extest command does not block or override the rams input pins; therefore, the rams internal state is still determined by its input pins. ? ? typically, the boundary scan r egister is loaded with the desire d pattern of data with the sample/preload command. then the extest command is used to output the boundary scan reg isters contents, in parallel, on the rams data output drivers on the falling edge of tck when the controller is in th e update-ir state. ? ? alternately, the boundary scan register may be loaded in parall el using the extest comman d. when the extest instruc - tion is selected, the sate of all the rams input and i/o pins, as well as the default values a t scan register locations not a sso - ciated with a pin, are transferred in parallel into the boundar y scan register on the rising ed ge of tck in the capture-dr state, the rams output pins drive out the value of the boundar y scan register location with w hich each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between t he tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is l oad ed in the instruction regist er, all ram outputs are forced to an inactive drive state (high - z) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 27/30 ? 2017, gsi technology preliminary jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj C 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj C 300 1 ua 2 tms, tck and tdi input leakage current i inlj C 1 100 ua 3 tdo output leakage current i olj C 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 v 5, 6 test port output low voltage v olj 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 v 5, 8 test port output cmos low v oljc 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be C 1 v < v i < v ddn +1 v not to exceed 2.9 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = C 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50: 30pf * jtag port ac test load * distributed test jig capacitance
gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 28/30 ? 2017, gsi technology preliminary jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 29/30 ? 2017, gsi technology gs82612qt19/37c e-350m/250m gs81332qt19/37ce-350m/250m gs8692qt19/37ce-350m/250m preliminary package dimensions?165- bump ccga (package ce) a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 index top view index bottom view 1.27 12.700.31 1.27 17.780.18 250.25 0.5(4x) ?0.8 (165x) seating plane 1.80.08 a b c d e f g h j k l m n p r 210.21 17.20.17 19.150.19
ordering information?gs i sigmaquad-ii+ sram org part number type package speed (m hz) t j * 288mb 8m x 36 gs82612qt37ce-350m 288mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 8m x 36 gs82612qt37ce-250m 288mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m 16m x 18 gs82612qt19ce-350m 288mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 16m x 18 gs82612qt19ce-250m 288mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m 144mb 4m x 36 gs81332qt37ce-350m 144mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 4m x 36 gs81332qt37ce-250m 144mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m 8m x 18 gs81332qt19ce-350m 144mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 8m x 18 GS81332QT19CE-250M 144mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m 72mb 2m x 36 gs8692qt37ce-350m 72mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 2m x 36 gs8692qt37ce-250m 72mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m 4m x 18 gs8692qt19ce-350m 72mb sigmaquad-ii+ b2 sram 165-bump ccga 350 m 4m x 18 gs8692qt19ce-250m 72mb sigmaquad-ii+ b2 sram 165-bump ccga 250 m note: m = military temperature range. sigmaquad-ii+ sram revision history file name format/content description of changes 82582qt37ce-rad_r1 creation of datasheet 2qt1937ce-rad_r1_01 content ? added process flow diagram on page 4 ? added op current data ? updated package drawing ? added 144mb and 72mb part numbers and related information ? updated part numbers to reflect new nomenclature ? added x18 configuration gs82612qt19/37c e-350m/250m gs81332qt19/37c e-350m/250m gs8692qt19/37ce-350m/250m specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 7/2017 30/30 ? 2017, gsi technology preliminary

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